As is known, the market requires mass storage memories that are able to store an ever increasing amount of data. Consequently, for some time research has been aimed at reducing the dimensions of individual cells so as to enable integration of an ever increasing number of cells in a single device. Another known solution consists in trying to store an increasing number of bits in a single cell, using multilevel storage techniques (the so-called “electrical enhancement”).
Both the solutions have, however, limitations linked both to theoretical limits and to difficulties in the design of memory arrays and of circuits designed to enable input and output of data into/from the memory arrays.
Other known solutions envisage the development of cells in a direction orthogonal to the traditionally used plane, comprising rows and columns. In particular, three-dimensional memory arrays have already been proposed, formed by superimposed levels of cells and thus provided also with a third dimension.
In this connection, U.S. Pat. No. 6,034,882 discloses a three-dimensional array wherein the memory cells are arranged on different levels and are formed by a selection element in series to a phase change element. The selection element is formed, for example, by a PN diode, a Schottky diode, a Zener diode, an SCR, a bipolar transistor or a field-effect transistor. The phase change element is formed, for example, by a fuse of dielectric material or of amorphous or polycrystalline silicon, by a ferroelectric capacitor, or by a Hall effect device. The memory array is thus formed by a grid of one-time programmable cells (OTP devices). This device is consequently unsuited to mass storage applications, wherein it is necessary to be able to erase and rewrite the cells a number of times.
U.S. Pat. No. 6,501,111 further describes a three-dimensional memory array that can be electrically programmed using as elementary cell a phase change resistance based upon the use of calcogenides. This solution thus uses a technology different from the classic ones employed for manufacturing electronic memories, which calls for the use of particular materials that are not common in the semiconductor industry and thus presents costs and levels of reliability that are still not well known.
Finally, U.S. Pat. No. 6,940,109 B2 describes a three-dimensional structure formed by transistors or memory cells and comprising a number of levels, each formed by a plurality of parallel lines extending each perpendicular to the lines of the level underneath it and the level above it. In the case of a memory array, each line is formed by a stack of layers, basically comprising: a bottom dielectric layer housing channel regions, each of which faces and is in electrical contact at its ends with two lines of the underlying level; a series of intermediate charge storage layers; and a series of top conductive layers in electrical contact with the channel regions of an overlying level. The two adjacent lines of an underlying level in electrical contact with a channel region of an overlying level thus constitute source and drain regions of a memory cell, while the top conductive layers of the overlying level form the gate of the same cell. In addition, the top conductive layers that form the gate of a cell of a given level form also the source and drain regions of cells of an overlying level.
In this way, each memory cell is formed so that it bestrides two levels and comprises at least three lines: two bottom, source and drain, lines and a top, gate, line.
Consequently, even though the structure enables a considerable increase in the density of cells per unit area, it does not efficiently exploit the available layers. In addition, the practical difficulties in alignment of the various layers, in particular of the ends of the channel regions to the bottom, source and drain, lines, causes actual manufacturing to be very difficult, require high production tolerances that partly nullify the gain in space achieved, and in practice cause the array difficult to produce.